Power Gating is yet another effective implementation employed in Low Power Designs. Unlike Clock Gating, which saves the dynamic power, Power Gating saves the leakage power. As we move from micron (i.e. greater than 90nm) technology nodes to sub-micron (i.e. less than 90nm) technology nodes, leakage power dissipation dominates the dynamic power dissipation. It is therefore employed very frequently in modern SoCs. We shall talk about the structure of a power gate in this post.
Consider any CMOS digital logic circuit consisting of Pull-Up Network (made from PMOS transistors) and Pull-Down Network (made from NMOS transistors), as shown in the figure.
At any point of time, if a direct path would exist from the power supply (VDD) and the ground (GND), the circuit would continue to dissipate leakage power. What is the possible turnaround? One can gate the power and ground terminals from the circuit when it is not intended to be used. That's what is accomplished by a power gate! Let's take a look at the circuit.
- During normal operation, SLEEP = 0. Both the PMOS and NMOS Sleep Transistors (in blue and green respectively) are ON. And we have Virtual Power Rails and Virtual Ground which ensure normal circuit operation.
- However, during periods of low activity, SLEEP = 1. Hence the Sleep Transistors turn OFF. And a direct path from power rails to ground is broken and hence no leakage power is dissipated due to the Pull-up and Pull-down networks.
Note that, during normal operation, Sleep Transistors contribute to some extra leakage power because they are still ON. Though, the leakage power due to these two transistors would be extremely small compared to that of the Pull-up and Pull-down networks, nevertheless, these transistors are custom designed in a way such that they have high Vt (the threshold voltage) to reduce any excess leakage power during normal mode of operation.
Can you also post a blog on basics of routing?
ReplyDeleteHi Vikrant. Please give a day or two. Will try to cover up the basics of Routing in a post shortly.
DeleteShouldn't the sleep transistors be high Vt? to have low leakage?
ReplyDeleteYes. You were right. Vt must be high to have low leakage. Thanks for pointing it.
DeleteWhat about the virtual power and virtual ground rails? Will they have the same values as original VDD and GND?
ReplyDeleteNo. They might be deviated due to IR drop.
DeleteJust wanted to understand , at what level is power gating implemented - transistor or block level ?? How is huge current and time requirement to restore virtual vdd during POWERON handled ?? And can you also extend on these and explain the concept of state retention and logic isolation
ReplyDeleteHi Niketh,
DeleteI believe that power gating is typically implemented at block level. By this I mean that one would typically like to gate the power supply to an entire block rather than just one standard cell.
Secondly, one power gating transistor (header and footer) may be shared by many standard cells together. The actual number is contingent upon the turn-on time. More the fan-out, more would be the turn-on time. Current for a single standard cell (this would be the leakage current) would be in the order of nW for let's say a 45nm technology cell. Even if a block has 1000 cells, the overall leakage power could easily be in uA, if not more.
Lastly, concept of state retention has been explained here: http://vlsi-soc.blogspot.in/2013/03/state-retention-power-gating.html
I'll try to cover up the concept of logic isolation some time later.
Thanks,
Naman
Do you have any idea on How the IR drop on PMOS & NMOS, which one will be less
ReplyDeleteIR drop is directly proportional to the resistance. If PMOS and NMOS are sized in a manner that the drive strength (alternatively resistance) pf the PMOS and NMOS is same then the IR drop would be the same.
DeleteHowever, for power gating, typically PMOS and NMOS are made minimum width HVT transistors. In that case, IR drop for PMOS would be more (by a factor of the mobility ratio of electrons/holes) than the IR drop of NMOS.
Good Point, Kartheek!
-Naman
So we know there is OFF transistor which causes leakage power. So when Header or footer switches are OFF then will it completely cut off leakage power or will it reduce leakage power due to high Vt?
ReplyDeleteHi Naman,
ReplyDeleteHow do you usually decide the number of power switches required in a design ?
The number of power gates is usually governed by the IR drop across power gates themselves. Plus the load of one power gate. For example, you can't load all the cells in your design using just 1 power gate. Because it won't be sufficient to drive so many gates without causing massive IR drop across gates, thereby affecting the robustness of the chip.
DeleteSometimes you have constraints like 1 PS would be good enough for a surrounding 10x10 micron sq. area. Or maybe 1 PS for every 20 logic gates. Likewise.
Is there any need to add power gating on clock tree? If it's not, is there any need to add isolation cell on clock gating path?
ReplyDeletewhich one is better PMOS OR NMOS for power gating?
ReplyDeleteAs far as I know PMOS is better as it's less leaky.
DeleteNaman or any expert -- Please give you inputs.
Can you tell us something about the drawbacks of power gating ?
ReplyDeleteWhen the power is gated OFF, how/ does the cell hold the state?
ReplyDelete