tag:blogger.com,1999:blog-2547531593106636954.post5462155983879649978..comments2024-03-27T00:15:35.843-07:00Comments on VLSI SoC Design: Power GatingNamanhttp://www.blogger.com/profile/07902192684048580280noreply@blogger.comBlogger18125tag:blogger.com,1999:blog-2547531593106636954.post-59136982853720310132023-06-13T18:46:37.159-07:002023-06-13T18:46:37.159-07:00When the power is gated OFF, how/ does the cell ho...When the power is gated OFF, how/ does the cell hold the state?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-83583492152011382992021-03-26T12:26:04.241-07:002021-03-26T12:26:04.241-07:00As far as I know PMOS is better as it's less l...As far as I know PMOS is better as it's less leaky.<br /><br />Naman or any expert -- Please give you inputs.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-47561049757666402392020-09-03T00:57:43.624-07:002020-09-03T00:57:43.624-07:00Can you tell us something about the drawbacks of p...Can you tell us something about the drawbacks of power gating ?syed osmanhttps://www.blogger.com/profile/15700329712377203800noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-24287711480421613572018-11-09T13:53:08.161-08:002018-11-09T13:53:08.161-08:00which one is better PMOS OR NMOS for power gating?...which one is better PMOS OR NMOS for power gating?Shivhttps://www.blogger.com/profile/02771374332533505506noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-82078850826519844502017-07-27T09:16:00.152-07:002017-07-27T09:16:00.152-07:00Is there any need to add power gating on clock tre...Is there any need to add power gating on clock tree? If it's not, is there any need to add isolation cell on clock gating path?SWARUP KUMAR PATTANAYAKhttps://www.blogger.com/profile/00130593484389396635noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-72196143461137257462017-03-05T11:24:18.895-08:002017-03-05T11:24:18.895-08:00The number of power gates is usually governed by t...The number of power gates is usually governed by the IR drop across power gates themselves. Plus the load of one power gate. For example, you can't load all the cells in your design using just 1 power gate. Because it won't be sufficient to drive so many gates without causing massive IR drop across gates, thereby affecting the robustness of the chip.<br />Sometimes you have constraints like 1 PS would be good enough for a surrounding 10x10 micron sq. area. Or maybe 1 PS for every 20 logic gates. Likewise.Namanhttps://www.blogger.com/profile/07902192684048580280noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-73483524831845468102017-03-05T07:41:14.015-08:002017-03-05T07:41:14.015-08:00Hi Naman,
How do you usually decide the number of...Hi Naman,<br /><br />How do you usually decide the number of power switches required in a design ?Santoshnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-25054170224563848582016-11-11T14:16:21.974-08:002016-11-11T14:16:21.974-08:00So we know there is OFF transistor which causes le...So we know there is OFF transistor which causes leakage power. So when Header or footer switches are OFF then will it completely cut off leakage power or will it reduce leakage power due to high Vt?Jackhttps://www.blogger.com/profile/00850432312633240678noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-32022890744156907302016-06-21T10:32:19.711-07:002016-06-21T10:32:19.711-07:00IR drop is directly proportional to the resistance...IR drop is directly proportional to the resistance. If PMOS and NMOS are sized in a manner that the drive strength (alternatively resistance) pf the PMOS and NMOS is same then the IR drop would be the same.<br /><br />However, for power gating, typically PMOS and NMOS are made minimum width HVT transistors. In that case, IR drop for PMOS would be more (by a factor of the mobility ratio of electrons/holes) than the IR drop of NMOS.<br /><br />Good Point, Kartheek!<br /><br />-NamanNamanhttps://www.blogger.com/profile/07902192684048580280noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-29625076866534588332016-06-21T01:01:46.684-07:002016-06-21T01:01:46.684-07:00Do you have any idea on How the IR drop on PMOS &a...Do you have any idea on How the IR drop on PMOS & NMOS, which one will be lesskartheekhttps://www.blogger.com/profile/00563957725790934234noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-83553256126893725092016-01-04T07:18:51.590-08:002016-01-04T07:18:51.590-08:00Hi Niketh,
I believe that power gating is typicall...Hi Niketh,<br />I believe that power gating is typically implemented at block level. By this I mean that one would typically like to gate the power supply to an entire block rather than just one standard cell. <br /><br />Secondly, one power gating transistor (header and footer) may be shared by many standard cells together. The actual number is contingent upon the turn-on time. More the fan-out, more would be the turn-on time. Current for a single standard cell (this would be the leakage current) would be in the order of nW for let's say a 45nm technology cell. Even if a block has 1000 cells, the overall leakage power could easily be in uA, if not more.<br /><br />Lastly, concept of state retention has been explained here: http://vlsi-soc.blogspot.in/2013/03/state-retention-power-gating.html<br />I'll try to cover up the concept of logic isolation some time later. <br /><br />Thanks,<br />NamanNamanhttps://www.blogger.com/profile/07902192684048580280noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-28621953167228163242016-01-03T12:17:11.994-08:002016-01-03T12:17:11.994-08:00Just wanted to understand , at what level is power...Just wanted to understand , at what level is power gating implemented - transistor or block level ?? How is huge current and time requirement to restore virtual vdd during POWERON handled ?? And can you also extend on these and explain the concept of state retention and logic isolation Nikethhttps://www.blogger.com/profile/03707833303050626105noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-63199640592861552182015-05-01T13:55:19.548-07:002015-05-01T13:55:19.548-07:00No. They might be deviated due to IR drop. No. They might be deviated due to IR drop. Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-5472950998740358652014-04-13T18:29:53.176-07:002014-04-13T18:29:53.176-07:00What about the virtual power and virtual ground ra...What about the virtual power and virtual ground rails? Will they have the same values as original VDD and GND?Sandshttps://www.blogger.com/profile/12422696926989504840noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-61201921871878847282013-11-03T03:02:54.531-08:002013-11-03T03:02:54.531-08:00Yes. You were right. Vt must be high to have low ...Yes. You were right. Vt must be high to have low leakage. Thanks for pointing it. Anonymoushttps://www.blogger.com/profile/05066949277808318582noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-30880389581603404672013-11-02T18:28:11.245-07:002013-11-02T18:28:11.245-07:00Shouldn't the sleep transistors be high Vt? to...Shouldn't the sleep transistors be high Vt? to have low leakage?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-51505498050221221432012-08-21T23:36:22.051-07:002012-08-21T23:36:22.051-07:00Hi Vikrant. Please give a day or two. Will try to ...Hi Vikrant. Please give a day or two. Will try to cover up the basics of Routing in a post shortly. Anonymoushttps://www.blogger.com/profile/05066949277808318582noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-35461735878195650232012-08-21T04:53:02.460-07:002012-08-21T04:53:02.460-07:00Can you also post a blog on basics of routing?
Can you also post a blog on basics of routing?<br />vikranthttps://www.blogger.com/profile/00228709367454077355noreply@blogger.com