Puzzle:
Tomorrow is the scheduled tape-out of your SoC. The target clock frequency for this SoC is 100 MHz (Time Period of 10 ns). However, there's only one setup violating path and you need to fix the timing by doing ECOs. Area is not a constraint.
Here's the circuit:
Points to note:
Mike posted the correct answer, and I'll just add a figure explaining the solution:
Tomorrow is the scheduled tape-out of your SoC. The target clock frequency for this SoC is 100 MHz (Time Period of 10 ns). However, there's only one setup violating path and you need to fix the timing by doing ECOs. Area is not a constraint.
Here's the circuit:
- My tape-out is tomorrow, I don't have the liberty of asking the RTL design team to change the architecture of the design.
- I have used the highest possible drive strength cells, and perhaps the lowest Vt flavor cells available in my standard cell library.
- There's no redundant logic in the path, it's been optimized well.
- I cannot add delay to the clock path of FF2 because doing so, the hold time of the scan chain connecting flops FF1 and FF2 would fail.
Please suggest ways to solve this timing violation. A rough image would be really helpful. I shall post my solution in a couple of days time.
Mike posted the correct answer, and I'll just add a figure explaining the solution:
