The Timing Optimization Problem

Puzzle:

Tomorrow is the scheduled tape-out of your SoC. The target clock frequency for this SoC is 100 MHz (Time Period of 10 ns). However, there's only one setup violating path and you need to fix the timing by doing ECOs. Area is not a constraint.

Here's the circuit:

Points to note:

• My tape-out is tomorrow, I don't have the liberty of asking the RTL design team to change the architecture of the design.
• I have used the highest possible drive strength cells, and perhaps the lowest Vt flavor cells available in my standard cell library.
• There's no redundant logic in the path, it's been optimized well.
• I cannot add delay to the clock path of FF2 because doing so, the hold time of the scan chain connecting flops FF1 and FF2 would fail.

Please suggest ways to solve this timing violation. A rough image would be really helpful. I shall post my solution in a couple of days time.

Mike posted the correct answer, and I'll just add a figure explaining the solution:

Puzzle: Vt Flavors of Standard Cells

Let's say you have the following flavors of standard cells (say NAND):

• NAND2_HVT_X2 (A two-input NAND gate, of High-Vt and drive strength 2).
• NAND2_HVT_X4
• NAND2_HVT_X8
• NAND2_LVT_X2
• NAND2_LVT_X4
• NAND2_LVT_X8

Can you help me arrange these cells in the decreasing order of their:

• Area
• Delay
• Leakage Power

Also please answer the following:

• Which cell(s) are you more likely to use on a setup-critical path?
• Which cell(s) are you more likely to use on a hold-critical path?
• Which cell(s) are you more likely to use in a chip with stringent low standby power specifications?

And the last question: which among the following do you think is responsible for different threshold voltage (Vt) characteristics of HVT and LVT cells:

1. Different doping profiles of HVT and LVT cells.
2. Different gate lengths of HVT and LVT cells. (Also called Gate Length Biasing).
3. Both of the above.
4. None of the above.

Hint: At some places, few quantities might be equal, so make sure you use equality instead of greater than.

Please post your answers in the comments below.

IDDQ Testing

IDDQ is the IEEE symbol for Direct Drain Quiescent Current and IDDQ Testing measures this current to discriminate between a good and a defective chip. But how could current be used to detect a fault? Read on!

IDDQ testing is gaining popularity among DFX (DFT, DFV, DFM etc condensed into DFX) engineers because it's cost effective and can detect faults which might be left undetected by traditional DFT techniques like the scan testing (stuck-at fault testing), atspeed testing (transition fault testing) or delay testing. IDDQ testing helps ascertain an extra degree of confidence that the manufactured chip is defect free and hence the defect level (the number of defective chips per million manufactured chips shipped to the customer) is low.

Principle: IDDQ testing is based on the principle that complimentary CMOS does not draw any current from the power supply when it's inputs are static (i.e. not switching). In reality, however, there exists a small leakage current which typically is orders of magnitude smaller than the switching current. By this definition, all CMOS circuits are 100% IDDQ testable. 

Faults detected by IDDQ tests:

• Bridging Faults: Shorts between two nodes causing a voltage contention because they are being driven by two conflicting voltages. Sometimes also referred to as stuck-on faults.
• Punch-through: Short between Drain and the source.
• Resistive Shorts
• Line and Gate Break Faults
• Source or Drain Break Faults
• Even some Delay Faults
• Latch-Up
• Stuck-open Faults,

Examples:

• Bridging Fault: If there exists a short (which could perhaps be because of some extra metal caused by process variations) between two wires which are driving opposite logic values, the voltage at the node might be at any intermediate level between VDD and 0. In the worst case it could be stuck at VDD/2, causing metastability at the flip-flop and hence a functional failure. If the two inverters in the circuit below are driven to opposite values, there's a current flow from the power supply of one inverter to the ground of another which would be typically in the range of tens of micro-amps (as opposed to nano-amps leakage current). This anomaly can be detected by IDDQ testing.

• Line Break Fault: If the input to any gate is broken (possibly because of mask misalignment), the input becomes floating. This floating input might attain any value which in the worst case might result in conduction through both NMOS and PMOS transistors, thereby resulting in a large current flow through the device.

The principle behind stuck-on faults, gate, drain and source break fault is fundamentally similar to the line break fault. 

Gate, drain and source break faults manifest inside the standard cells where there exists an open at either one or more of the transistor terminals, again causing a floating node and hence an unknown voltage value resulting in high current!

Refer to the post on Latch-Up to understand how does Latch-Up result in a high-current flow through the CMOS device. This high current flowing through the device can be propagated to the power rail and detected using IDDQ test vectors.

Caveat of IDDQ Testing: 

• There might exist a few corner cases where a good circuit might be identified as a faulty by IDDQ testing. Such cases can be reverse-engineered to ascertain to be false, however, it might take a lot of effort and debug-time. Discussing such cases is beyond the scope of this blog post.
• As mentioned earlier, IDDQ testing can be used for CMOS circuits. Dynamic Logic has been gaining a lot of attention in the recent years in high-speed applications. Dynamic Logic circuits cannot be tested using IDDQ testing because it exhibits precharge property where the output capacitance is charged every time in the precharge phase irrespective of the value at inputs (even if they are static!)

Comparison with other testing methodologies:

• While other testing methodologies like scan and atspeed rely on detecting the voltage level at the node in question which is being tested for a desired fault, IDDQ testing senses current levels. 
• Traditional testing methodologies rely on the two pillars of DFT namely: controlability and observability as the sensitized fault (controlability) needs to be propagated to the output (observability), in order to detect a fault. In IDDQ testing, all faults are propagated to the power supply which is much easier to do so. Hence, typically, only 2-3 test vectors are sufficient to achieve a 50% fault coverage for IDDQ testing.
• Scan and atspeed testing require ATE (Automatic Test Equipment) to apply test patterns and receive the output of the DUT (Device Under Test). IDDQ tests require an off-chip current monitoring device, in addition to the ATE.

References: 

• IDDQ Made Easy. CMOS IDDQ Test Methodology by Bob Duell, Systems Science Inc.
• IDDQ Testing Outline. Lecture Slides by Dr. Wenben Jone, University of Cincinnati.

Puzzle: Wire Delay

Technical Tidbit:

You have a long wire of let's say length L. And it has the net delay of 100ps. Now you split the wire into two equal halves of length 0.5L each and insert a buffer at the center of the wire. The delay of buffer is 25ps. What is the total delay of the system: (half wire+ buffer + half wire)?

Option a: 50+25+50= 125ps
Option b: 25+25+25=75ps
Option c: 25+25+50=100ps
Option d: 50+25+25=100ps

Choose the right option, and please give a short explanation.

Thanks!

Puzzle: Best Performing Processor

You have 3 different processors:

• Single Cycle CPU
• Multi Cycle CPU
• Pipelined CPU

All the three processors, somehow magically, are clocked at the same rate. Can you arrange these processors in the descending order of the performance and a small explanation for the answer?

Puzzle: Ring Oscillators

Ring Oscillators are very commonly used circuits in SoCs, where they find their use in Voltage Controlled Oscillators used inside the PLLs, and also used as Silicon odometer circuits- which are used to track various parameters of the device like variation of timing with ageing etc.

It is also a well-known fact that ring oscillators have odd number of inverters connected in form of a chain, as shown below:

And the frequency of oscillations is given by the expression:

f = 1/(2NT)

N= Number of inverters (odd)

T= Propagation delay of a single inverter

Can you comment on the below circuit? Maybe an expression for it's oscillation frequency? Or perhaps any analytical expression (without bothering about the intricacies of various transistor parameters) for the voltage? Assume the operating voltage to be 1V.

Please post your answers here. I'd be happy to share the solution and my thought process in a couple of days.

Inverter vs Buffer Based Clock Tree

A buffer is nothing but two inverters connected back to back. Does it make any difference if the CTS (Clock Tree Synthesis) is done using buffers or inverters? What exactly are the pros and cons and what factors would the backend design engineers take into account while deciding how to build their clock trees? I'm gonna answer these questions in this post.

An inverter based clock tree: 

To keep things simple and pertinent to the discussion, let's assume that we are using only a single kind of inverter (i.e. of let's say drive X) to build our clock trees. And all the inverters are placed equidistant from each other. The scenario is shown in Fig. 1. Advantage of using an inverter based clock tree is that the high pulse width and the low pulse width would be symmetrical. For the clock signal, this is a critical requirement, especially for SoCs which have a high interaction between the positive and negative edge triggered flip-flops.

Figure 1: Inverter Based Clock Tree giving equal rise and fall times

A buffer based clock tree:

While theoretically, one can create a buffer using two identical inverters connected back to back, that is generally not the way buffers are designed while designing the standard cell libraries. To save area, the first buffer is typically of a lower drive strength and is placed very closed to the second inverter. The second inverter, however, is of higher drive strength. 

Figure 2: Buffer Based Clock Tree. Buffer is formed by connecting two invertes back to back

One must also notice that the delay of first inverter is dominated by the load of the second inverter because the wire length between these two inverters is very small, hence one can neglect the wire cap. But for the second inverter, the load comprises of the wire cap as well as the input cap of the next buffer. This introduces an asymmetry in the rise and fall delays, and hence the high and low pulse widths of the clock signal. 

Figure 3: Difference in high and low pulse widths

For applications which have a very stringent requirement on the clock high and low pulse widths, one might prefer to use an inverter based clock tree over the buffer based clock tree.

Can we do something to make the buffer based clock tree work? The answer is yes! Let's take a look:

If we balance the load seen by first inverter and the load seen by the second inverter, we might be able to achieve equal rise and fall times, and hence equal high and low pulse widths for the clock transition signal.

In this approximation, we have modeled the wire in form of a T-model. And inverter is modeled using distributed RC model with it's "on" resistance and the diffusion capacitance.

Figure 4: RC delay model for inverters and wire

To have the equal pulse widths for high and low times, the RC delay observed by the first inverter must be equal to the RC delay of the second inverter.

Rchn,1 (CD,1 + CG2) = Rchp,2 (CD,2 + Cwire + CG,1) + Rwire/2 (Cwire + CG,1) + Rwire/2 (CG,1)

If this equation is satisfied, one can say with a fair degree of confidence that the high and low pulse widths would be approximately equal. The resistance and capacitance of the wire is the function of its length and the same can be conveyed by the standard cell library designer to the backend designers.

While most standard cell library vendors provide a symmetrical buffer, there could well be a difference of a few pico-seconds in the buffer rise and fall delay, which creates a difference in the high and low pulse widths. The variation in the duty cycle increases for deeper clock trees!

A simple way to mitigate the problem is to insert an inverter in the middle point of the buffer-cased clock tree. The major challenge, however, lies in finding this middle point. This ensures that high and low pulse widths of the clock reaching at the sink pins of flip-flops is indeed the same!

Figure 5: Inserting an inverter to maintain high and low pulse widths