Simultaneous Setup-Hold Critical Node

I've got this question multiple times- How do we fix timing violations on paths that have at least one node which is both setup critical and hold critical simultaneously. To answer that question, one must realize that (generally speaking) for the same PVT and same RC corner, there cannot be paths where all nodes are simultaneously setup and hold critical. 

Let's take an example:

Test Case

Now, if we buffer at node C, path from B to C which was already setup critical will start violating.

Buffering at C

If we buffer at Node A, the path from A to D which was already setup critical would start violating.

What shall we do here now? Any suggestions? Thoughts? I'd like to hear from you and I'll post the right answer (at least one of the right answers soon!). Just like always, looking forward to engage in the comments section below. 

The Legend of Synchronizer

Long time ago, there were two warriors: Clock Domain 1 and Clock Domain 2. Each had their respective clocks CLK-1 and CLK-2 which they contended to be the master of their own will! The frequency and the phase relationship of the two clocks were independent of each other.

In absence of any such relationship, there is a possibility of the two clock edges being precariously close that could in turn cause a timing violation. The metastable output of the FF-2 could pass on to the entire system and disrupt the entire computation of the chip. FF-S steps in to resolve the impasse and urges the two clock domains to have a deterministic relationship between their clocks.

But the two clock domains refuse to budge! Neither of them were willing to curtail the freedom of their clocks which they deeply cherished! 

Here the FF-S sacrifices its own output and offers a solution to the clock domains.

That's how the FF-S ensured the prosperity of the entire SoC by suffering a metastability at it's own output. And since then it's been called The SYNCHRONIZER Flop! Note that it is necessary to connect the synchronizer flop's clock to the clock of the second domain.

Over the years, there's been a practice of using up to three such synchronizer flops depending upon the application.

I'll talk about the concept of Mean Time Before Failure (MTBF) which is very closely related to metastability shortly.

Puzzle: Fixing Timing Violation

Timing Violation can manifest due to a plethora of reasons. And it is important for an STA Engineer to understand the violating path and model the constraints properly before providing them to the Synthesis/PnR tools for optimization. Unnecessary optimization should be avoided because:

• To save on the die area;
• To save on the leakage power;
• To prevent unnecessary congestion.

The figure below shows a scenario. Assume the clock period to be 8ns and the setup time of the capture flop (here, FF3) be 0ns and the clock-to-Q delay of the launch flops (here, FF1 & FF2) be 0ns. The violating path is shown in the figure. The negative slack is 1ns. 

How would you fix the above violation? Please note that there are many possible solutions; but one only solution adheres to the above discussed constraints of leakage power, area and congestion.

Sample Problem on Setup and Hold

In the post Timing: Basics, we discussed about the basics of setup and hold times. Why is it necessary to meet the setup and hold timing requirements. And how frequency affects setup but does not affect hold.

Let us understand the concept with an example:

I hope the above waveforms are self explanatory.
Setup Slack in the above case (as inferred from the waveforms as well) is:

Setup Slack = Tclk - T(clk-2-q) - Tdata - T(su,FF2)

If this setup slack is positive, we say that setup time constraint is met. Note that setup slack depends upon the clock period and hence in turn frequency at which your design is clocked.

Let us consider hold timing:

Hold Slack = Tdata + T(clk-2-q) - T(ho,FF2)

As evident from the above equation, hold slack is independent of the frequency of the design.

Note:

• Setup is the next cycle check, we would take the setup time T(su,FF2) of FF2 into account while finding setup slack at input pin of FF2.
• Hold time is the same cycle check, we would take the hold time T(ho,FF2) of FF2 into account while computing the hold slack at input pin of FF2.

Try and grasp this example. I shall introduce the concept of clock skew next.