Channel Length vs Gate Length

Till a few months back, I assumed that channel length and gate length were same terms used interchangeably. However, one of the classes that I took at USC cleared this doubt and I'm very thankful to my professor for explaining the subtle difference between the two.

The figure above shows the cross-section of an NMOS with it's source, drain, gate. Let's talk about the difference between gate length, channel length and the diffusion length.

While fabricating a MOS device, typically the poly gate is grown first using the minimum feature size mask which is characteristic of a particular technology node. After this, the source and drain are formed by ion-implantation of Phosphorus (n+). This is referred to as self-aligned process. After ion-implantation, there is some side diffusion of the implanted ions because of which, the n+ region extends up to a small width below the gate. This is referred to as the diffusion length or the diffusion width. The effective distance between the drain and the source where the channel would eventually be formed and the actual length an electron would travel from source to drain is called the Effective Channel Length! I encourage you to read up more about the steps in CMOS Fabrication for better understanding. 

As evident from the above figure:

Channel Length = Gate Length - 2 x (Diffusion Length)

Well, that was theory! Now some practical discussion. :)

When we say that we have let's say a 28 nm technology node. Which of the above would be 28 nm? Well, it would be the GATE LENGTH! As pointed above, gate corresponds to the minimum feature size mask which is characteristic of a particular technology node!

Now, let's say, this NMOS is operating in the saturation regime, and there's no pinch off yet. If you wish to find the saturation current flowing through the device, you'll have to use the channel length in the formula for the drain current which is a quadratic function of the gate-to-source voltage. 

How do we find this channel length? For older technology nodes (like 250 nm), this diffusion used to be negligible as compared to the gate length. However, for advanced sub-micron technology nodes, the side diffusion length is typically 10% of the gate length. (Actual numbers may vary from one manufacturer to another). So, for 28 nm technology node, you might expect the actual channel length to be in the order of 20-22 nm.

Feature Size of Transistors

The feature size of any semiconductor technology is defined as the minimum length of the MOS transistor channel between the drain and the source. The technology node has been scaling year by year. From early 2000s it has shrunk from 180nm to 22nm designs today (2014).

You would have probably noticed that the technology scaling has followed:

180nm -->> 130nm -->> 90nm -->> 65nm -->> 40nm -->> 28nm --> 22nm...

Ever wondered who decides these numbers? Are these arbitrary or there's some inherent logic behind these numbers? Let's see.

In early 1970s, Gordon Moore of Intel Corp. predicted that the number of transistor on a an integrated circuit would double itself in approximately 18-24 months. This prediction has proven to be accurate as scaling of technology continues unabated even after 40 years! Well, it's mainly because Moore's law has set out a challenge and a roadmap for designers to keep the scaling going! 

You might ask yourself, why scaling? Here's why:

• If double number of transistors can be incorporated on the same area, it means we get double (roughly) functionality for the same cost!
• Alternatively, with scaling of technology, the same functionality will be available at roughly half the cost! 
• Moreover, smaller the channel length, faster would be the transient response of the transistors which would translate into better performance!

The goal of every design company now is to double the number of transistors on their integrated circuits with each technology. As you would notice, the numbers above from 180nm to 130nm to 90nm scale down by roughly a factor of 0.7. What's so special about 0.7?

If the feature size of the transistor is scaled by 0.7, the area would be scaled by a factor of 0.7²=0.49 =~ 0.5. That means if we scale our feature sizes by a factor of roughly 0.7, we would be able to pack twice the number of transistors on the same area as the previous technology!