March 12, 2013

State Retention Power Gating

The post titled Power Gating demonstrated the implementation of a Power Gating Cell and how it helps in minimizing the leakage power consumption of an SoC. Make sure you go through it once more. The basic rationale is to cut the direct path from the battery (VDD) to ground (GND). Though efficient in saving the leakage power, the implementation discussed suffers from one major drawback! It does not retain the state! That means, once power of the SoC is restored, the output of the power gated cell goes to 'X'. You can't really be sure whether it is logic 1 or a logic 0. Do care? Yes! Because if this X propagates into the design, the entire device can go into a metastable state! In order to prevent such a disastrous situation: the system software can simply reset the SoC. That would boot-up from scratch and make sure that all the devices are initialized. 

This means, every time I decide to power gate a portion of my SoC, I'll have to reset that power gated portion once power is returned. This imposes a serious limitation to the application of the Power Gate discussed in the last post. How about designing one power gate which retains the state? But convince yourself that in order to do so, you'd need to spend, though small, some leakage power. Let's call this structure: State Retention Pseudo Power Gate. The term "pseudo" signifies that it would consume a little leakage power contrary to the previous structure which doesn't. But at the same time, you no longer need to reset the power gated portion of the SoC, because the standard cells retain their previous data!! Enough said! Let's discuss the implementation.

The above circuit has two parts. 
  • The one inside the red oval is same as the normal power gating structure. 
  • The one inside green box (on the right) is the additional circuitry required to enable this device to retain it's state.
Operation: Let's say before going into the SLEEP mode, the device had the output as logic 1. After entering the SLEEP mode (power off), the sleep transistors come into action and cut the power and ground rails of the device and hence save the leakage power. But the logic on the right (in green rectangle) is still ON! The output of the inverter would now become OUTPUT', i.e., logic 0. This would in turn enable the PMOS transistor Q1 and output would be restored back to logic 1.
Same is true when the output would be logic 0 before power gating. In that case the NMOS transistor Q0 would come into action to help the output node retain it's data.

Note that: All this while, when the device is in sleep mode, the output node would continue to leak. By adding the additional circuitry, as demonstrated, we are basically trying to create a feedback loop, which again helps in retaining the state. The hit, of course, is the leakage power of 4 transistors. However, the standard cell logic (in red oval) is usually bulky. Even a simple 2-input NAND gate has 4 transistors itself. And higher order input would have more! Same technique can be applied to any sequential device like a Flip Flop, latch or even a clock gating integrated cell.


  1. Can this same circuit be used to design a State Retention Flip Flop as well?

  2. Yes. The same circuit can be employed to design a state retention flip flop as well!

  3. Hello Naman,

    I have few doubts/questions on this implementation.

    If the PUN and Q1 are ON, then OUTPUT is being driven by multiple drivers. How can we prevent this?
    Can we replace the four transistor circuit by a state retention cell used in tri-state logic gates?

    1. Hi Karthik,

      If the PUN is ON, then OUTPUT would be '0'. The gate of Q1 would be '1'. And therefore Q1 would be OFF. There can never be a scenario where both PUN and Q1 are ON simultaneously.

      Could you please share the circuit for tri-state logic gate?

    2. Hi Naman,

      retention register placement, where they place? will they replace all register with retention register of power down block, can you please elaborate about it and switch cell

      Plz share some details about it.


    3. Hi Gayatri,

      One might want to replace all registers of a power down block with retention registers, but that is rarely the case. Because it would mean higher area.

      Typically, one would want to retain the values of configuration registers which decide the mode a particular SoC is working in. Or perhaps some other critical registers which can help the normal operation once the SoC is powered up again.

      What do you want to know about switch cell? Switch cell is basically a power switch. It will turn on/off the power. Input would be power, output would be power and it would have a control signal which will basically control the switch. Retention registers or perhaps any version of header/footer transistors provide a more granular control over power gating. But power switch would just turn off the power of let's say an entire block.


    4. Hello Naman,

      If the PUN is ON, then the OUTPUT is 1 so the o/p of the retention cell, P is 0 and so the pmos Q1 is ON and the OUTPUT is indeed being driven by two drivers. Do we have to maintain the equal Vdd for both the circuits?
      In that case is the retention cell hvt, which is helping in leakage reduction?

    5. Ideally yes, we need to maintain the equal VDD for both circuits. Why would anyone want anything otherwise?
      And yes, we're basically saving leakage of the purported bulky PDN, PUN of the base structure and retaining the state at the cost of burning leakage power in 4 transistors which can be made HVT to minimize the leakage.

  4. Is there any need of retention cell on clock tree path?