In the post, Clock Gating, I described the rationale behind gating the clock and the repercussions one might face if the clock is not gated properly.
To recapitulate, for clock gating:
- Rationale: Saving the dynamic power of the Flip Flops.
- Repercussion (if not done properly): Glitch in the clock tree; and hence metastability at the flop outputs.
Clock can be gated in many ways. Some require more precautions than others. We model those "precautions" in the form of constraints for the EDA tool to understand. And that's what are called Clock Gating Checks.
Let's consider them all one by one.
The same scenario also appeared in the puzzle titled: Identify Issue with Circuit Topology. The solution for problem, and for the above constraint to be met would be that the launching flop should be a negative edge triggered flop.
You might argue that a positive edge triggered flop with sufficient delay might also solve the purpose. But note that, that scenario would vary with the PVT corners. It might very well be a case that the delay is sufficient in the worst case PVT, and not in the base case PVT; which would be very difficult to achieve!
- AND Gate based Clock Gating: As we discussed in the last post, to prevent any glitch from being propagated at the output of AND Gate based clock gating, the enable signal must switch only when the clock is low. Consider the following scenario and note the setup and hold checks for it.
You might argue that a positive edge triggered flop with sufficient delay might also solve the purpose. But note that, that scenario would vary with the PVT corners. It might very well be a case that the delay is sufficient in the worst case PVT, and not in the base case PVT; which would be very difficult to achieve!
- OR Gate Based Clock Gating: To prevent any
glitch being propagated to the output of an OR gate based clock gating,
the enable should toggle only when the clock is high. The figure below
depicts the setup and hold checks in an OR gate based clock gating.
We shall discuss the clock gating checks for a multiplexer in the next post. Till then, try to grasp this post!
Here for clock gating you are using flip-flops and on the blog for clock gating you have used latches to make clock gating circuit.
ReplyDeleteWhich one will be best for designing???
And thanks for such a good and informative blog. :)
Hi there.
DeletePlease note that it is not a flip-flop that I have used for clock gating. Flip-flop is just sending out the enable signal! Irrespective of whether I use OR gate, AND gate, or a CGIC (made from a latch), I'll need an enable signal that would invariably come from a sequential element.
So, I reckon, your question is which one is better? Using AND/OR gates or a CGIC?
In this case, please note that we have a half-cycle clock gating hold check for an AND gate which imposes a constraint on the hardware that enable should only come from a negative edge triggered flop. For an OR Gate, we have a half cycle clock gating setup check, which again imposes a constraint that enable should come from a positive edge triggered flop. However, if we use CGIC, there is no such constraint.
Apart from such a liberty, CGICs are generally more robust! Hence, it's always preferable to use a CGIC for clock gating. You might want to check other posts especially, "Faulty Clock Gating: How Not to Gate the Clock" to get more insight. Please let me know in case you have any query!
Thanks for your kind words of appreciation! It surely motivates me to write more. :)
I am a little confused. I too have the same doubt. For clk gating , the en signal is from a negative latch to ensure transition happens only in the low of the clk signal to avoid glitches. The flop here from which the en signal is coming out. Is it for the same purpose?
DeleteThe topic is meant to be saying how the enable signal should be sent to clock gating logic. To take out your confusion replace and gate with CGIC.
DeleteHi ,
ReplyDeletewhere do we specify this constraint (clock gate setup/hold?
Hi Suresh,
DeleteSome clock gating checks are implicitly inferred. Like those checks while using a clock gating integrated cell. However, for other clock gating checks involving gates (AND, OR, NAND, OR or even a MUX), the clock gating checks need to be explicitly defined in the SDC assuming a safe margin that would probably be dictated by the technology node you're working on and the actual robustness of the clock gating desired.
Please let me know if something is still not clear.
Thanks,
Naman