tag:blogger.com,1999:blog-2547531593106636954.post2270232994683556683..comments2024-03-27T00:15:35.843-07:00Comments on VLSI SoC Design: Inverter vs Buffer Based Clock TreeNamanhttp://www.blogger.com/profile/07902192684048580280noreply@blogger.comBlogger16125tag:blogger.com,1999:blog-2547531593106636954.post-72433347870049578112024-03-20T05:08:17.796-07:002024-03-20T05:08:17.796-07:00Hi Naman,
But still I have seen many designs with...Hi Naman, <br />But still I have seen many designs with buffer based clock tree mixed with inverter in order to fix the min pulse or min period violation.<br />Since Buffer has better drive strength as compared to inverter which will help to recover area as well as power, hence designs are using buffer based clock tree mixed with few inverter (inverters are basically used to fix min pulse).<br />Please comment here, if anything you are not agree with.Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-53112683315939797752019-11-12T08:15:41.243-08:002019-11-12T08:15:41.243-08:00We normally use LVT type buf/inv while building cl...We normally use LVT type buf/inv while building clock trees. because LVT type will have lesser process variation. Manojnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-70763159275168252342019-10-30T09:32:28.084-07:002019-10-30T09:32:28.084-07:00So, industry wide clock trees are built using buff...So, industry wide clock trees are built using buffers. What could be the reason? Also, can you comment which Vt buffers/inverters are preferred in clock tree and why?<br />Sanjeevnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-29826972724458844412019-07-23T02:55:30.996-07:002019-07-23T02:55:30.996-07:00Amazing Article, Thanks for sharing!
How to Choose...Amazing Article, Thanks for sharing!<br /><a href="https://www.justwebworld.com/how-to-choose-the-best-inverter-for-your-home/" rel="nofollow">How to Choose the Best Inverter </a>gopipatelhttps://www.blogger.com/profile/04314175811935973396noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-88627509022064644742019-06-15T04:50:57.340-07:002019-06-15T04:50:57.340-07:00Good work. thank you for such kind of great inform...Good work. thank you for such kind of great information. <a href="https://daytum.com/outdoorhunt" rel="nofollow">For More</a><br />reenahttps://www.blogger.com/profile/07386209398086968739noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-7953816487685618792019-01-11T00:03:57.386-08:002019-01-11T00:03:57.386-08:00Nice Blog. I like it..
Inverter BatteryNice Blog. I like it..<br /><br /><a href="http://electronicwale.com/inverter-battery/" rel="nofollow">Inverter Battery</a> electronicwalehttps://www.blogger.com/profile/09420681480458282378noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-6592471713566586362018-10-23T03:02:45.044-07:002018-10-23T03:02:45.044-07:00This comment has been removed by a blog administrator.Suganyahttps://www.blogger.com/profile/05373759708268987725noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-70788010811049081792018-06-03T16:25:31.665-07:002018-06-03T16:25:31.665-07:00Hi Naman,
Thanks for the amazing blogs! At device...Hi Naman,<br /><br />Thanks for the amazing blogs! At device level, is inverter a better noise filter than a buffer? I was trying to analyze using NMh and NMl values, but am a little confused. Can you help? Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-5495635496396110462015-11-23T23:26:01.038-08:002015-11-23T23:26:01.038-08:00Hi Naman,
Can you explain bit more...how by insert...Hi Naman,<br />Can you explain bit more...how by inserting a inverter...it will result in equal rise and fall trasition and leads to 50% duty cycle...Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-85980064227784350002015-10-05T08:03:08.939-07:002015-10-05T08:03:08.939-07:00hi guys
jus to add few points.
1. u dnt need ex...hi guys<br /><br />jus to add few points.<br /><br />1. u dnt need extra inverter to drive negative edge flop<br />2. when you are keeping equidistant inverters. consider equidistant buffers<br />3.rise/fall slew would definitely be better in inverter than buffersharukhhttps://www.blogger.com/profile/15157392288721470231noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-74480659976024274232015-09-09T05:12:22.612-07:002015-09-09T05:12:22.612-07:00hey, somebody help me to calculate how much distan...hey, somebody help me to calculate how much distance can a buf/inv can drive ?<br />can we get these value from library itself ?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-17192075733685935742014-12-24T04:05:33.200-08:002014-12-24T04:05:33.200-08:00Hi Naman,
Thanks for a quick reply!
I am not su...Hi Naman,<br /><br />Thanks for a quick reply! <br /><br />I am not sure why a negative edge triggered flop will need an extra inverter. That flop will just trigger on the falling edge of the clock (which comes out of the buffer output pin, and not from inside of the buffer), that's it!<br /><br />A buffer and inverter both can have almost equal rise/fall times, it doesn't matter if it's inverter or buffer.<br /><br />I am not clear enough on the buffer vs inverter tree tradeoffs, but the depiction of asymmetrical clock pulse using figure 3 is not correct for sure. You have to consider a falling edge also to the input of the buffer. What you have shown is a whole clock pulse generated out of the rising edge alone!<br /><br />Thanks,<br />SagarSagar Patelhttps://www.blogger.com/profile/06590768817182682118noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-15335573705541008712014-12-23T23:58:13.769-08:002014-12-23T23:58:13.769-08:00Hi Sagar,
While I agree with the contention that ...Hi Sagar,<br /><br />While I agree with the contention that unequal resistances (arising due to difference in mobility of holes and electrons) of PMOS and NMOS would give rise to unequal rise and fall times, in this post, I assumed the widths of the two devices have been scaled in ratio of the mobility. Note that the rise and fall time is not just contingent upon the resistance of the devices, but also on the load that the PMOS observes (while charging), or perhaps NMOS observes (while discharging).<br /><br />You've brought an interesting point that I need not observe inside of the buffer! That is absolutely correct! However the point that we need to observe only the input ad output pins of buffer is partially correct. If in my design, I have all the flops working at positive edge of the clock (or all of them at negative edge of the clock), I indeed need to observe the input and output pins of the buffer only. However, the whole discussion of asymmetric duty cycle arises when we have interaction between positive and negative edge triggered flops. Even in this case I need not observe the transition at the internal pin of the buffer, but I'll need an extra inverter feeding the negative edge triggered flop. And there would lie the difference in fall and rise times.<br /><br />I'm sure you'd have more to comment. And honestly, your question did put me in a spot of bother. And I'm not quite sure whether this answer will pacify you. I'd encourage you to reply back either way! :)<br /><br />Thanks,<br />NamanNamanhttps://www.blogger.com/profile/07902192684048580280noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-91624713423407259502014-12-23T23:06:38.474-08:002014-12-23T23:06:38.474-08:00Hi Naman,
I am confused with Figure 3. You are tr...Hi Naman,<br /><br />I am confused with Figure 3. You are trying to observe falling edge inside of the buffer! That's not relevant at all I think. What we need to observe is input and output pins of buffer only to see the transition times.<br /><br />The inequality of rise and fall time result from inequality of resistance of PMOS and NMOS of the buffer ot inverter. That is, while charging the load (rise edge), the current goes through PMOS, and while discharging the load (fall edge), current goes through NMOS, and hence we see different rise/fall times. This can be mitigated by using different channel widths for PMOS and NMOS.<br /><br />Please correct me if I am wrong.Sagar Patelhttps://www.blogger.com/profile/06590768817182682118noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-89427724414460856492014-12-18T19:59:46.362-08:002014-12-18T19:59:46.362-08:00Thanks Babul! :)Thanks Babul! :)Namanhttps://www.blogger.com/profile/07902192684048580280noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-85320350180752372332014-12-18T09:12:06.887-08:002014-12-18T09:12:06.887-08:00Thanks for simplifying the underlying reasons in c...Thanks for simplifying the underlying reasons in choosing buffer-based or inverter-based clock tree. :)Babul Anunayhttps://www.blogger.com/profile/07685579858969399875noreply@blogger.com