tag:blogger.com,1999:blog-2547531593106636954.post698448364253291919..comments2024-03-27T00:15:35.843-07:00Comments on VLSI SoC Design: Clock Gating CheckNamanhttp://www.blogger.com/profile/07902192684048580280noreply@blogger.comBlogger6125tag:blogger.com,1999:blog-2547531593106636954.post-21917989254443752442019-08-31T19:32:18.827-07:002019-08-31T19:32:18.827-07:00The topic is meant to be saying how the enable sig...The topic is meant to be saying how the enable signal should be sent to clock gating logic. To take out your confusion replace and gate with CGIC.vinayhttps://www.blogger.com/profile/16862422865574454151noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-61384609406988228722017-10-17T14:21:14.704-07:002017-10-17T14:21:14.704-07:00I am a little confused. I too have the same doubt....I am a little confused. I too have the same doubt. For clk gating , the en signal is from a negative latch to ensure transition happens only in the low of the clk signal to avoid glitches. The flop here from which the en signal is coming out. Is it for the same purpose?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-60835225108810251762016-02-26T13:16:08.508-08:002016-02-26T13:16:08.508-08:00Hi Suresh,
Some clock gating checks are implicitl...Hi Suresh,<br /><br />Some clock gating checks are implicitly inferred. Like those checks while using a clock gating integrated cell. However, for other clock gating checks involving gates (AND, OR, NAND, OR or even a MUX), the clock gating checks need to be explicitly defined in the SDC assuming a safe margin that would probably be dictated by the technology node you're working on and the actual robustness of the clock gating desired.<br /><br />Please let me know if something is still not clear.<br /><br />Thanks,<br />NamanNamanhttps://www.blogger.com/profile/07902192684048580280noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-30881374271955269162016-02-25T22:38:39.186-08:002016-02-25T22:38:39.186-08:00Hi ,
where do we specify this constraint (clock g...Hi , <br />where do we specify this constraint (clock gate setup/hold?<br />Sureshhttps://www.blogger.com/profile/16381974534286655926noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-28161733968813626282013-09-21T08:36:17.659-07:002013-09-21T08:36:17.659-07:00Hi there.
Please note that it is not a flip-flop ...Hi there.<br /><br />Please note that it is not a flip-flop that I have used for clock gating. Flip-flop is just sending out the enable signal! Irrespective of whether I use OR gate, AND gate, or a CGIC (made from a latch), I'll need an enable signal that would invariably come from a sequential element.<br /><br />So, I reckon, your question is which one is better? Using AND/OR gates or a CGIC?<br />In this case, please note that we have a half-cycle clock gating hold check for an AND gate which imposes a constraint on the hardware that enable should only come from a negative edge triggered flop. For an OR Gate, we have a half cycle clock gating setup check, which again imposes a constraint that enable should come from a positive edge triggered flop. However, if we use CGIC, there is no such constraint.<br /><br />Apart from such a liberty, CGICs are generally more robust! Hence, it's always preferable to use a CGIC for clock gating. You might want to check other posts especially, "Faulty Clock Gating: How Not to Gate the Clock" to get more insight. Please let me know in case you have any query!<br /><br />Thanks for your kind words of appreciation! It surely motivates me to write more. :)Anonymoushttps://www.blogger.com/profile/05066949277808318582noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-45493574645167331292013-09-20T23:44:14.437-07:002013-09-20T23:44:14.437-07:00Here for clock gating you are using flip-flops and...Here for clock gating you are using flip-flops and on the blog for clock gating you have used latches to make clock gating circuit.<br />Which one will be best for designing??? <br />And thanks for such a good and informative blog. :)JAPANhttps://www.blogger.com/profile/03711810826798714267noreply@blogger.com