tag:blogger.com,1999:blog-2547531593106636954.post4074075211019692080..comments2024-03-27T00:15:35.843-07:00Comments on VLSI SoC Design: Multi-Cycle Paths: Perspective & IntentNamanhttp://www.blogger.com/profile/07902192684048580280noreply@blogger.comBlogger10125tag:blogger.com,1999:blog-2547531593106636954.post-20488477069877964122021-11-15T01:29:11.142-08:002021-11-15T01:29:11.142-08:00What is the difference between Timing MCPs and Fun...What is the difference between Timing MCPs and Functional MCPs? Anonymoushttps://www.blogger.com/profile/11085976711192747248noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-28686464445625138492021-08-01T04:07:19.862-07:002021-08-01T04:07:19.862-07:00If Ive one or 2 critical paths in the design, can...If Ive one or 2 critical paths in the design, can I apply MCP? If not, why? And what are the complications if we apply MCP for these 2 paths. JJRhttps://www.blogger.com/profile/11178069135520606457noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-16322874865708243362019-01-11T07:44:05.860-08:002019-01-11T07:44:05.860-08:00Great Post !! I have one doubt. While doing Setup ...Great Post !! I have one doubt. While doing Setup check for MCPs we check after every 2 clock cycle (as per above explanation). What about Hold check? Do we check at one clock cycle prior to setup check edge or at the launch edge?<br />Muralihttps://www.blogger.com/profile/02807428216219837628noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-30574824938948453842017-04-08T13:05:09.791-07:002017-04-08T13:05:09.791-07:00Could you kindly elaborate on 'configurable im...Could you kindly elaborate on 'configurable implementation of multicycle paths'?Subhechchahttps://www.blogger.com/profile/12976694200848058994noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-52597843402387884872014-02-21T08:23:11.416-08:002014-02-21T08:23:11.416-08:00MCPs could be defined wrt to any clock. See, as I ...MCPs could be defined wrt to any clock. See, as I mentioned in the post, MCPs are governed by architecture. The STA folks must understand the intent that's the designer implies and then apply the MCP which could be wrt to fast clock or slow clock; launch clock or the fast clock (or maybe both!).<br /><br />Synthesis tools are not cognizant of MCPs or false paths. Although majority of the MCPs are false paths are governed by the design about which only a designer can tell, the synthesis (or for that matter the timing tool itself) cannot even identify some obvious false paths as the one depicted in this problem: http://vlsi-soc.blogspot.in/2013/02/puzzle-fixing-timing-violation.html<br /><br />One must always understand the intent behind MCPs or false paths and then model then accordingly.<br /><br />I hope I was able to answer your query! :)<br /><br />Thanks!Anonymoushttps://www.blogger.com/profile/05066949277808318582noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-18285530544316619142014-02-21T08:18:35.114-08:002014-02-21T08:18:35.114-08:00Yes. The timing tools (like ETS and Primetime) wou...Yes. The timing tools (like ETS and Primetime) would always try to time those paths at the highest frequency, i.e. f. We need to explicitly define in the MCP: the number of MCPs wrt to fast or the slow clock and the through pin (optional).Anonymoushttps://www.blogger.com/profile/05066949277808318582noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-84359563575496971182014-02-21T03:56:22.229-08:002014-02-21T03:56:22.229-08:00Another doubt, should we define MCP with respect t...Another doubt, should we define MCP with respect to the launch clock or the destination clock ? By any chance, will the synthesis tool will help us identify the possible MCP and False paths ?Vasanthhttps://www.blogger.com/profile/00488080332796973829noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-1268997355984492582014-02-21T03:32:12.444-08:002014-02-21T03:32:12.444-08:00Do we need to declare the path as MCP, even if the...Do we need to declare the path as MCP, even if the clock with 'f' freqency and 'f/2' are derived from the same clock source ? Vasanthhttps://www.blogger.com/profile/00488080332796973829noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-20608738552997483442013-04-20T06:14:42.081-07:002013-04-20T06:14:42.081-07:00Hi Danny. Thanks for the kind words of appreciatio...Hi Danny. Thanks for the kind words of appreciation. :) I am glad you liked the post! :)Anonymoushttps://www.blogger.com/profile/05066949277808318582noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-40382236456415305402013-04-19T21:11:45.136-07:002013-04-19T21:11:45.136-07:00Nice! I must confess that was really an eye-opener...Nice! I must confess that was really an eye-opener. All this while, I used to think that all those paths which can't be met in single cycle, are potential MCPs! <br /><br />Thanks!Dannynoreply@blogger.com