tag:blogger.com,1999:blog-2547531593106636954.post1263085981835663131..comments2024-03-27T00:15:35.843-07:00Comments on VLSI SoC Design: Tuning CTS RecipeNamanhttp://www.blogger.com/profile/07902192684048580280noreply@blogger.comBlogger15125tag:blogger.com,1999:blog-2547531593106636954.post-44745078538011123302021-12-21T19:36:35.439-08:002021-12-21T19:36:35.439-08:00thanks for your sharing. very useful information.thanks for your sharing. very useful information.Anonymoushttps://www.blogger.com/profile/15856526059828641445noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-286340327224511442021-07-03T23:27:35.314-07:002021-07-03T23:27:35.314-07:00some clock structures and gating logic demands tha...some clock structures and gating logic demands that. NEELthinkinghttps://www.blogger.com/profile/15441329577932974040noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-45849761604195031942021-07-03T23:26:28.579-07:002021-07-03T23:26:28.579-07:00power , area , OCV. power , area , OCV. NEELthinkinghttps://www.blogger.com/profile/15441329577932974040noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-70034010323842156852021-05-22T02:45:44.683-07:002021-05-22T02:45:44.683-07:00Thank you again for all the knowledge you distribu...Thank you again for all the knowledge you distribute,Good post. I was very interested in the article, it's quite inspiring I should admit. I like visiting you site since I always come across interesting articles like this one. <a href="https://seletron.com/it/" rel="nofollow">centralina aggiuntiva moto</a><br />Willeum Bruchhttps://www.blogger.com/profile/08481762472047055252noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-22315260470584442382020-02-19T22:13:56.939-08:002020-02-19T22:13:56.939-08:00Always so interesting to visit your site.What a gr...Always so interesting to visit your site.What a great info, thank you for sharing. this will help me so much in my learning <a href="https://djstowingnyc.com/" rel="nofollow">new york towing</a><br />Harryhttps://www.blogger.com/profile/16072410961048022282noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-79074906372123674772020-01-15T12:08:15.669-08:002020-01-15T12:08:15.669-08:00what is disadvantage of having high clock insertio...what is disadvantage of having high clock insertion delay on timing violations assuming clock skew is balanced? Sunil kumarhttps://www.blogger.com/profile/10819050432981558699noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-45458889337546916092019-09-23T07:53:37.602-07:002019-09-23T07:53:37.602-07:00Is there anyone who know what is the theoretical m...Is there anyone who know what is the theoretical meaning of multi-fanout skew balancing?Anonymoushttps://www.blogger.com/profile/12070268930845259399noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-79706188704357491692019-03-14T15:02:59.627-07:002019-03-14T15:02:59.627-07:00Hi
4step ( dividec by clock as stop pin) . If i ...Hi <br /> 4step ( dividec by clock as stop pin) . If i define the divider clock pin as stop pin,divider will be balanced with the master clock sinks. But this is stop pin, divider clock sinks have be to balanced separately by defining the cts root pin at the outptut of the divider. Is that true ?Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-64560675540982031922018-07-22T17:05:14.627-07:002018-07-22T17:05:14.627-07:00Hi Naman,
This maybe slightly off topic, but what...Hi Naman,<br /><br />This maybe slightly off topic, but what would be the reason for using a clock signal as data? (exclude pin condition).Anonymousnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-29704380081322187022017-11-06T08:11:07.869-08:002017-11-06T08:11:07.869-08:00Hi Naman, in CTS spec file we will specify max_tra...Hi Naman, in CTS spec file we will specify max_tran & max_cap requirements right, on what basis we will specify those limits.Anonymoushttps://www.blogger.com/profile/05031577706496510523noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-44559757313966986882017-10-04T21:37:14.519-07:002017-10-04T21:37:14.519-07:00Hi Naman, This will surely standout as one of THE ...Hi Naman, This will surely standout as one of THE best post on CTS online. Cant thank you enough for answering many of my questions at one go through this post.<br /><br />PKAnonymoushttps://www.blogger.com/profile/08644626840939263441noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-2324510134369827332017-04-30T22:41:49.368-07:002017-04-30T22:41:49.368-07:00That isn't a naive question. This question is ...That isn't a naive question. This question is indeed a hallmark of someone with an experienced eye! :)<br />The first sign that would prompt you to dig deeper into the CTS flow would be the timing violations. Now, timing violations may pop up due to high local clock skew, which could be an artifact of high clock latency of some sequentials, which could possibly be because they were placed far away than the rest. Or it could be that you see many clock buffers clustered in a very small area which means that CTS didn't add them for maintaining transition on clock network, but probably added them to balance the longest and shortest path of the same clock. In this case you'd again need to debug the longest network.<br /><br />Another case could be hold violations due to OCVs on uncommon clock path. You need to see the point of divergence, and argue whether it could be moved far away from the source to increase the common clock path.<br /><br />You need to analyze all fan-outs, fan-out count, hard IPs etc. These will give you some insight into what the problem could be. An experienced engineer would be able to debug quicker using their instincts (and experience, of course, both go hand-in-hand). You need to be prepared to fire experiments, do a lot of hit and trial and keep on improving stuff incrementally! :)<br /><br />Namanhttps://www.blogger.com/profile/07902192684048580280noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-20878221453177345472017-04-29T15:27:27.632-07:002017-04-29T15:27:27.632-07:00Excellent insight into CTS. Very well explained wi...Excellent insight into CTS. Very well explained with comprehensive user cases.<br /><br />I have a question which might be very naive. <br /><br />How do you analyse a particular CTS situation, where you could use one of the above use cases you have explained. Santoshnoreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-81288333935734176152017-04-16T13:38:16.658-07:002017-04-16T13:38:16.658-07:00You have mentioned 'we would be interested in ...You have mentioned 'we would be interested in reducing the skew between same clock groups'.<br />Shouldn't we be considering the global skew as well? Wouldn't a huge global skew result into hold violations in scan mode?Subhechchahttps://www.blogger.com/profile/12976694200848058994noreply@blogger.comtag:blogger.com,1999:blog-2547531593106636954.post-4488844039722210562017-04-16T13:25:40.683-07:002017-04-16T13:25:40.683-07:00In sequential clustering, how are we supposed to k...In sequential clustering, how are we supposed to know whether there will be increase in the number of setup/hold violations?<br />I mean, if we go for tightly binding the cells and then going for the placement run, we might figure out that things went haywire (costing us runtime). In that case is there some technique to figure it out beforehand?Subhechchahttps://www.blogger.com/profile/12976694200848058994noreply@blogger.com